1. Field of the Invention
The invention generally relates to integrated circuits that use multiple voltage biases, and in particular, to interface circuitry for translating signals from one voltage domain to another.
2. Description of the Related Art
Many integrated circuits or “chips” employ multiple power supplies or biases. For example, a digital core of a chip may operate from a 1.2V supply, while a low-voltage differential signaling (LVDS) transmitter in an input/output (I/O) portion of the chip may operate from a 3.3V supply. Terms that have been used to describe these integrated circuits include “split-voltage” or “dual-voltage.” This difference in voltage requires an interface to translate data and control signals between the two or more voltage domains. A level-shifter is used to raise signal levels from a lower voltage domain to a higher voltage domain or even between two independent domains with the same voltage potential. A level shifter circuit is typically not needed when traversing from a high voltage domain to a lower voltage domain
One challenging aspect for a multiple-voltage integrated circuit is that the sequencing of the multiple power supplies or biases can be unpredictable. For example, a multiple-voltage integrated circuit can be used in a very wide variety of applications, and the sequencing of the power supplies can vary. For example, one power supply cannot be guaranteed to power-up before another. Typically, both power supplies are ramped up at approximately the same time. However, due to physical delays in the two sources, either supply could come up slightly before the other. This can temporarily cause a level-shifter circuit to generate an unknown or unintended output state. Passing this unknown value can be detrimental to intended circuit performance. In addition, relatively large on-chip currents can be drawn, potentially damaging the device, if the output of the level-shifter is mid-rail (i.e., between a low level and a high level) or if the level-shifter's unknown state causes contention down-stream. For example, in a complementary MOS (CMOS) circuit, a mid-rail input can result in mutual conduction from the complementary pairs of transistors, which results in relatively large on-chip currents.
Conventional level shifters draw relatively high currents from the supply during IDDQ (quiescent supply current) testing when one or more of the power supplies are ramping up relatively slowly and/or when the power supplies are started with relative delay. This can disadvantageously prevent the use of IDDQ compliance testing to uncover circuit faults in manufacturing. Even a relatively small static current can add up to a substantial amount of current when many level shifters are present in a device.
FIG. 1 illustrates a conventional level shifter. The digital signal is translated from input (IN) to output (OUT) from a first, typically lower voltage domain (VDDL) to a second, typically higher, voltage domain (VDDH). The non-inverting buffer 102 and the inverter 104 provide complementary drive signals as inputs to a first NMOS transistor 106 and a second NMOS transistor 108. The first NMOS transistor 106 and the second NMOS transistor 108 are coupled to a first PMOS transistor 110 and a second PMOS transistor 112.
A problem exists when the lower voltage source (VDDL) is not available, and the higher voltage source (VDDH) is ramping up slowly to its normal operating level. In this circumstance, the level shifter can generate a mid-rail voltage output, which can be damaging to circuits further downstream that are also powered by the higher voltage source (VDDH). When VDDL is not powered on, the outputs of the non-inverting buffer 102 and the inverter 104 are the same potential (low) such that the same potential is provided as inputs to both the first NMOS transistor 106 and the second NMOS transistor 108. This is contrary to the complementary drive that should be provided. For example, when the input to the second NMOS transistor 108 is low, the output (OUT) should be driven to VDDH by activation of the second PMOS transistor 112. However, because both the first NMOS transistor 106 and the second NMOS transistor 108 are off, and the gates of the PMOS transistors 110, 112 are not driven, the output (OUT) is typically not pulled to a valid logic level (full rail for a static condition). The output (OUT) typically floats “mid-rail” to within a threshold of VDDH, which can lead to harmful mutual conduction and excessive currents in downstream circuitry.